The present invention relates to comparator circuits, and in particular to high speed comparator circuits having a wide dynamic range.
A comparator is a circuit that compares two input signals, and generates an output signal that indicates which of the two input signals is larger. Comparator circuits are used, for example, to convert analog input signals into digital values. High speed, accuracy and a wide dynamic range are important characteristics of comparators. However, it is difficult to achieve all three characteristics at the same time.
FIG. 1 is a block diagram showing a prior art comparator circuit 100 that compares two analog input voltages VIN1, and VIN2, and generates full swing output signals VOUT1 and VOUT2 that indicate the larger of input voltages VIN1, and VIN2. Comparator circuit 100 includes a current source 110, a differential input circuit 120, and a CMOS latch 130. Current source 110 is controlled by a current source bias signal VCSB to draw a bias current IA+B from differential input circuit 120. Differential input circuit 120 generates currents IA and IB that are proportional to input voltages VIN1, and VIN2, and whose sum is equal to bias current IA+B CMOS latch 140 is controlled by clock signals xcfx861 and xcfx862 to sequentially operate in reset, comparison, and latch operating modes. The reset mode is used to initialize CMOS latch 130. During the comparison and latch modes, currents IA and IB are used to set output signals VOUT1 and VOUT2 in a first state (VOUT1 is high and VOUT2 is low), or a second state VOUT1 is low and VOUT2 is high), thereby indicating which of input signals VIN1, and VIN2 is larger. Additional details regarding the operation of comparator circuit 100 are provided below.
FIG. 2 is a simplified schematic diagram showing a CMOS implementation of comparator circuit 100.
As indicated in FIG. 2, current source 110 includes an n-channel transistor M1 connected between input circuit 120 and ground. A gate terminal of n-channel transistor M1 is connected to receive an externally generated bias signal VCSB, which is used to set bias current IA+B.
Input circuit 120 includes a differential input transistor pair M2 and M3 that are connected in parallel between CMOS latch 130 and current source 110. Current IA is generated in a first conductor 122 that is connected between transistor M2 and a node NA of CMOS latch 130. Current IB is generated on a second conductor 124 that is connected between transistor M3 and a node NB of CMOS latch 130. The gate terminals of transistors M2 and M3 are respectively connected to input voltages VIN1, and VIN2.
CMOS latch 130 includes a p-channel flip-flop 132 connected between a system voltage source and nodes NA and NB, an n-channel flip-flop 134 connected between ground and a second pair of nodes NC and ND, a pair of p-channel pass transistors M6 and M7 connected between flip-flops 132 and 134, a p-channel switch M8 connected between nodes NA and ND, and a pair of n-channel precharge transistors M11 and M12 respectively connected to nodes NC and ND. P-channel flip-flop 132 includes p-channel transistors M4 and M5 that are respectively connected between the system voltage source and nodes NA and NB, with the gate terminal of transistor M4 connected to node NB and the gate terminal of transistor M5 connected to node NA. P-channel pass transistors M6 and M7 are controlled by second clock signal xcfx862. P-channel pass transistor M6 is connected between node NA and node NC (which is connected to output terminal VOUT1), and p-channel pass transistor M7 is connected between node NB and node ND (which is connected to output terminal VOUT2). P-channel switch M8 has a gate terminal connected to receive first clock signal xcfx861 . N-channel flip-flop 134 includes n-channel transistors M9 and M10. Transistor M9 is connected between node NC and ground and has a gate terminal connected to node ND, and transistor M10 is connected between node ND and ground and has a gate terminal connected to node NC. Precharge transistors M11 and M12 have gate terminals connected to receive second clock signal xcfx862, with precharge transistor M11 connected between node NC and ground, and precharge transistor M12 connected between node ND and ground.
FIGS. 3(A) and 3(B) are timing diagrams showing the voltage levels of clock signals xcfx861 and xcfx862 during the reset mode (i.e., time interval T1-T2), comparison mode (i.e., time interval T2-T3), and latch mode (i.e., time interval T3-T4) of CMOS latch 130. During the reset mode (time interval T1-T2), first clock signal xcfx861 is low and second clock signal xcfx862 is high. During the comparison mode (time interval T2-T3), both clock signals xcfx861 and xcfx862 are high. During the latch mode (time interval T3-T4), first clock signal xcfx861 is high and second clock signal xcfx862 is low.
Operation of comparator circuit 100 will now be described with reference to FIGS. 2, 3(A), and 3(B).
During the reset mode, the low clock signal xcfx861 turns on switch M8, thereby equalizing nodes NA and NB and resetting p-channel flip-flop 132. In addition, the high clock signal xcfx862 turns off p-channel pass transistors M6 and M7, and turns on n-channel precharge transistors M11 and M12, thereby pulling down nodes NC and ND and resetting n-channel flip-flop 134 to ground (i.e., both output signals VOUT1 and VOUT2 are low). Because p-channel pass transistors M6 and M7 are turned off, node NA is isolated from node NC, and node NB is isolated from node ND. Under these conditions, the sum of the currents flowing through transistors M4 and M5 (i.e., currents IA and IB) is equal to IA+B and is independent of input signals VIN1, and VIN2 (assuming input signals VIN1, and/or VIN2 is/are within the dynamic range). Similarly, during the reset mode, the voltage at nodes NA and NB is equal to a reset voltage that is independent of input signals VIN1, and VIN2.
At the beginning of the comparison mode (time T2 in FIGS. 3(A) and 3(B)), both clock signals xcfx861 and xcfx862 are high. Accordingly, first clock signal xcfx861 turns off (opens) switch M8, thereby disconnecting nodes NA and NB and initiating the operation of p-channel flip-flop 132. Immediately after time T2, if input signal VIN1, is less than input signal VIN2, then the current through p-channel transistor M5 is greater than the current through p-channel transistor M4, thereby causing the voltage at node NA to increase from the reset voltage and the voltage at node NB to decrease from the reset voltage. Conversely, when input signal VIN1 is greater than input signal VIN2, then the current through p-channel transistor M5 is less than the current through p-channel transistor M4, and the voltage at node NA decreases from the reset voltage while the voltage at node NB increases from the reset voltage.
At the beginning of the latch mode (time T3), clock signal xcfx862 switches low, thereby turning off precharge transistors M11 and M12, and turning on (closing) pass transistors M6 and M7. The voltage gain between nodes NA and NB, which is caused by the difference between the currents through p-channel transistors M4 and M5 of p-channel flip-flop-132 during the comparison mode, is transferred through pass transistors M6 and M7, respectively, to n-channel flip-flop 134. If input signal VIN1, is less than input signal VIN2, then the signal passed through n-channel pass transistor M6 to node NC is greater than the signal passed through n-channel pass transistor M7 to node ND, thereby latching flip-flop 134 in a first state (i.e., output signal VOUT1 is high, and output signal VOUT2 is low). Conversely, if input signal VIN1 is greater than input signal VIN2, then the signal passed through n-channel pass transistor M6 to node NC is less than the signal passed through n-channel pass transistor M7 to node ND, thereby latching flip-flop 134 in a second state (i.e., output signal VOUT1 is low, and output signal VOUT2 is high).
A problem associated with prior art comparator circuit 100 is that at least one of the two input signals (i.e., either VIN1 or VIN2) must be significantly greater than ground in order for differential input circuit 120 to reliably toggle CMOS latch 130, thereby limiting the dynamic range of comparator circuit 100. Specifically, if both input voltages VIN1, and VIN2 are negative or near-ground, then neither transistor of differential input transistor pair M2 and M3 is turned on (i.e., identical currents IA and IB are applied to CMOS latch 130 during the comparison mode). Consequently, output signals VOWT and VOUT2 fail to indicate which of the negative or near-ground input signals VIN1 and VIN2 is greater (i.e., more positive).
What is needed is a comparator circuit that can compare two negative or near-ground input signals.
The present invention is directed to a comparator circuit that transforms a difference between two input voltage signals into differential branch currents that are determined by a difference between the two input voltage signals, but are independent of an average of the two input voltage signals. The differential branch currents are then applied, for example, to a CMOS latch that operates in a conventional manner to generate output signals indicating which of the two input voltage signals is greater. Because the differential branch currents are independent of the average input voltage, the comparator circuit of the present invention is able to compare two negative or nearground input voltage signals, thereby overcoming the limitations of prior art comparator circuits.
In accordance with an embodiment of the present invention, a comparator circuit includes an adaptive bias voltage circuit, a cascode stage, and a conventional CMOS latch.
The adaptive bias voltage circuit generates a bias voltage that is directly proportional to an average of the two input voltage signals. The adaptive bias voltage circuit includes a current source, a n-channel transistor having drain and gate terminals connected to the current source, and a pair of p-channel transistors that are connected between a source terminal of the n-channel transistor and ground. The two input voltage signals are respectively applied to the gate terminals of the p-channel transistors. The bias voltage is generated at the gate/drain terminals of the n-channel transistor. In operation, when the average of the two input voltage signals is negative or near-ground, conductance through the p-channel transistors is relatively high, thereby pulling the bias voltage to a relatively low level. Conversely, when the average of the two input voltage signals is positive (i.e., above ground), conductance through the p-channel transistors is relatively low, thereby causing the bias voltage to be relatively high.
The cascode stage utilizes the bias voltage generated by the adaptive bias voltage circuit to generate branch currents that are determined solely by a difference between the two input voltage signals (i.e., the branch currents are independent of the average input voltage). The cascode stage includes a first branch that includes a first p-channel transistor and a first n-channel transistor connected in series between the CMOS latch and ground, and a second branch that includes a second p-channel transistor and a second n-channel transistor connected in series between the CMOS latch and ground. The bias voltage is applied to the gate terminals of the first and second n-channel transistors, and the two input voltages are applied to the gate terminals of the first and second p-channel transistors. When the bias voltage is relatively low (indicating that the average input voltage is negative or near-ground), the resistance of the n-channel transistors is relatively high, thereby restricting the current flow through the p-channel transistors (which would otherwise be relatively high due to the negative or near-ground average input voltage). Conversely, when the bias voltage is relatively high (indicating that the average input voltage is positive), the resistance of the n-channel transistors is relatively low, thereby increasing the current flow through the p-channel transistors (which would otherwise be relatively low due to the positive average input voltage). In this manner, the differential branch currents through the first and second branches of the cascode stage are independent of the input voltages signals, thereby providing a greater dynamic range than that provided by prior art comparator circuits.